Special Topic: Recent Progress of Fundamental Research on Post-Moore Novel Devices
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From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits
Zhang, Zhaoyang; Chen, Jinwu; Chen, Xi; Guo, An; Wang, Bo; Xiong, Tianzhu; Kong, Yuyao; Pu, Xingyu; He, Shengnan; Si, Xin; Yang, Jun
Sci China Inf Sci, 2023, 66(10): 200403
Keywords: artificial intelligence; compute-in-memory; static random access memory
Cite as: Zhang Z Y, Chen J W, Chen X, et al. From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. Sci China Inf Sci, 2023, 66(10): 200403, doi: 10.1007/s11432-023-3800-9
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An efficient path delay variability model for wide-voltage-range digital circuits
Shan, Weiwei; Cui, Yuqiang; Dai, Wentao; Liu, Xinning; Guo, Jingjing; Cao, Peng; Yang, Jun
Sci China Inf Sci, 2023, 66(2): 129401
Keywords: modeling; PVT variations; delay variability; digital integrated circuit; FO4 inverter chain
Cite as: Shan W W, Cui Y Q, Dai W T, et al. An efficient path delay variability model for wide-voltage-range digital circuits. Sci China Inf Sci, 2023, 66(2): 129401, doi: 10.1007/s11432-021-3407-2
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Keywords: convolutional neural networks; stochastic computing; sparse neural networks; energy-efficient accelerator; high reconfigurability; spatial parallelism
Cite as: Xia Z H, Wan R, Chen J N, et al. Reconfigurable spatial-parallel stochastic computing for accelerating sparse convolutional neural networks. Sci China Inf Sci, 2023, 66(6): 162404, doi: 10.1007/s11432-021-3519-1
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Keywords: power and data telemetry; inductive link; implantable medical device; brain-computer interface; phase-locked-loop; binary-phase-shift keying; power transfer efficiency
Cite as: Chen M Y, Pan L M H, Lin Q Y, et al. A 70%-power transmission efficiency, 3.39 Mbps power and data telemetry over a single 13.56 MHz inductive link for biomedical implants. Sci China Inf Sci, 2023, 66(2): 122406, doi: 10.1007/s11432-022-3563-9
Special Topic: AI Chips and Systems for Large Language Models
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CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts
Han, Shihao; Liu, Sishuo; Du, Shucheng; Li, Mingzi; Ye, Zijian; Xu, Xiaoxin; Li, Yi; Wang, Zhongrui; Shang, Dashan
Sci China Inf Sci, 2024, 67(10): 200405
Keywords: mixture-of-experts; computing-in-memory; neural architecture search; resistive random-access memory; static random-access memory
Cite as: Han S H, Liu S S, Du S C, et al. CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts. Sci China Inf Sci, 2024, 67(10): 200405, doi: 10.1007/s11432-024-4144-y
Special Topic: AI Chips and Systems for Large Language Models
POSITION PAPER
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Large circuit models: opportunities and challenges
Chen, Lei; Chen, Yiqi; Chu, Zhufei; Fang, Wenji; Ho, Tsung-Yi; Huang, Ru; Huang, Yu; Khan, Sadaf; Li, Min; Li, Xingquan; Li, Yu; Liang, Yun; Liu, Jinwei; Liu, Yi; Lin, Yibo; Luo, Guojie; Pan, Hongyang; Shi, Zhengyuan; Sun, Guangyu; Tsaras, Dimitrios; Wang, Runsheng; Wang, Ziyi; Wei, Xinming; Xie, Zhiyao; Xu, Qiang; Xue, Chenhao; Yan, Junchi; Yang, Jun; Yu, Bei; Yuan, Mingxuan; Young, Evangeline F. Y.; Zeng, Xuan; Zhang, Haoyi; Zhang, Zuodong; Zhao, Yuxiang; Zhen, Hui-Ling; Zheng, Ziyang; Zhu, Binwu; Zhu, Keren; Zou, Sunan
Sci China Inf Sci, 2024, 67(10): 200402
Keywords: AI-rooted EDA; large circuit models; LCMs; multimodal circuit representation learning; circuit optimization
Cite as: Chen L, Chen Y Q, Chu Z F, et al. Large circuit models: opportunities and challenges. Sci China Inf Sci, 2024, 67(10): 200402, doi: 10.1007/s11432-024-4155-7
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An analysis of TinyML@ICCAD for implementing AI on low-power microprocessor
Li, Guoqing; Zhang, Jingwei; Zhang, Meng; Li, Tuo; Chen, Tinghuan; Yang, Jun
Sci China Inf Sci, 2024, 67(4): 149402
Keywords: Low-end microprocessor; Tiny machine learning; Artificial intelligence; Benchmark; Ventricular arrhythmia detection
Cite as: Li G Q, Zhang J W, Zhang M, et al. An analysis of TinyML@ICCAD for implementing AI on low-power microprocessor. Sci China Inf Sci, 2024, 67(4): 149402, doi: 10.1007/s11432-023-3934-y
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SWG: an architecture for sparse weight gradient computation
Wu, Weiwei; Tu, Fengbin; Li, Xiangyu; Wei, Shaojun; Yin, Shouyi
Sci China Inf Sci, 2024, 67(2): 122405
Keywords: CNN; training; gradient computation; sparsity; architecture
Cite as: Wu W W, Tu F B, Li X Y, et al. SWG: an architecture for sparse weight gradient computation. Sci China Inf Sci, 2024, 67(2): 122405, doi: 10.1007/s11432-022-3807-9
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A reconfigurable Wilkinson power divider based on transmission-line phase shifter for 5G new radio
Yu, Yiming; Zhang, Xiaoning; Zhao, Chenxi; Liu, Huihua; Wu, Yunqiu; Kang, Kai
Sci China Inf Sci, 2023, 66(12): 229407
Keywords: CMOS; 5G; multi-band; reconfigurable; phase shifter; transmission line; Wilkinson power divider; new radio
Cite as: Yu Y M, Zhang X N, Zhao C X, et al. A reconfigurable Wilkinson power divider based on transmission-line phase shifter for 5G new radio. Sci China Inf Sci, 2023, 66(12): 229407, doi: 10.1007/s11432-022-3827-4
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Keywords: low-noise amplifier; D-band; SiGe; gain-noise plane; collaborative optimization
Cite as: Xu Z C, Ni M H, Xie Q, et al. Collaborative gain and noise optimization: a design of 150-173-GHz cascode LNA with 22.3 dB gain and 6.92 dB NF based on the gain-noise plane. Sci China Inf Sci, 2023, 66(10): 209401, doi: 10.1007/s11432-022-3622-1
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Keywords: motion estimation; optical flow; motion energy; hardware Random Forests; VLSI hardware system
Cite as: Shi C, He J X, Pundlik S, et al. Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests. Sci China Inf Sci, 2023, 66(5): 159401, doi: 10.1007/s11432-021-3473-1
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Keywords: ECG; flexible dry electrodes; analog front-end; abnormality detection ASIC; wireless transmission
Cite as: Xu X Z, Suo Y X, Zhao Y, et al. A dry-electrode enabled ECG-on-Chip with arrhythmia-aware data transmission. Sci China Inf Sci, 2025, 68(2): 122405, doi: 10.1007/s11432-024-4196-0
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Keywords: computing in memory; neural network accelerators; non-volatile memory; hardware non-ideal characteristics; software-hardware co-design
Cite as: Han L X, Huang P, Wang Y J, et al. Mitigating methodology of hardware non-ideal characteristics for non-volatile memory based neural networks. Sci China Inf Sci, 2025, 68(2): 122403, doi: 10.1007/s11432-023-4021-y
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Analysis and solution of streak effect in high dynamic range CMOS image sensors
Zha, Wanbin; Xu, Jiangtao; Ao, Jinghua; Nie, Kaiming; Gao, Zhiyuan
Sci China Inf Sci, 2025, 68(1): 119404
Keywords: CMOS image sensor; high dynamic range; streak effect; dual conversion gain; pixel design
Cite as: Zha W B, Xu J T, Ao J H, et al. Analysis and solution of streak effect in high dynamic range CMOS image sensors. Sci China Inf Sci, 2025, 68(1): 119404, doi: 10.1007/s11432-024-4198-8
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Software-defined process-near-memory architecture using 3D hybrid bonding integration
Xu, Anlin; Deng, Chenchen; Zhu, Jianfeng; Wang, Yao; Wei, Shaojun; Liu, Leibo
Sci China Inf Sci, 2025, 68(1): 112402
Keywords: software-defined chips; process near memory; energy efficiency; dynamic reconfiguration; domain specific
Cite as: Xu A L, Deng C C, Zhu J F, et al. Software-defined process-near-memory architecture using 3D hybrid bonding integration. Sci China Inf Sci, 2025, 68(1): 112402, doi: 10.1007/s11432-023-3965-1
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Keywords: ADC; reconfigurable; amplifier; optimization; sigma delta
Cite as: Zhu Z M, Song J J, Liang Y H. A 10-kHz 12-16-bit reconfigurable zoom ADC with pole optimization technique and floating current-starved amplifier. Sci China Inf Sci, 2024, 67(12): 229403, doi: 10.1007/s11432-024-4189-1
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Keywords: CMOS image sensors; single-slope ADC; adaptive ramp signal generator; correction of inconsistent error in ramp signals; column fixed pattern noise
Cite as: Guo Z J, Li L, Xu R M, et al. A high consistency ramp circuit design method for negative feedback adaptive adjustment mechanism applied to large area array CMOS image sensors. Sci China Inf Sci, 2024, 67(12): 229401, doi: 10.1007/s11432-024-4165-x
Special Topic: AI Chips and Systems for Large Language Models
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SpikingMiniLM: energy-efficient spiking transformer for natural language understanding
Zhang, Jiayu; Shen, Jiangrong; Wang, Zeke; Guo, Qinghai; Yan, Rui; Pan, Gang; Tang, Huajin
Sci China Inf Sci, 2024, 67(10): 200406
Keywords: spiking neural networks; natural language understanding; spiking Transformer; spike-based attention; multi-step encoding; ANN-to-SNN distillation
Cite as: Zhang J Y, Shen J R, Wang Z K, et al. SpikingMiniLM: energy-efficient spiking transformer for natural language understanding. Sci China Inf Sci, 2024, 67(10): 200406, doi: 10.1007/s11432-024-4101-6
Special Topic: AI Chips and Systems for Large Language Models
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Hardware-oriented algorithms for softmax and layer normalization of large language models
Li, Wenjie; Lyu, Dongxu; Wang, Gang; Hu, Aokun; Xu, Ningyi; He, Guanghui
Sci China Inf Sci, 2024, 67(10): 200404
Keywords: large language model; softmax; layer normalization; hardware architecture; Transformer
Cite as: Li W J, Lyu D X, Wang G, et al. Hardware-oriented algorithms for softmax and layer normalization of large language models. Sci China Inf Sci, 2024, 67(10): 200404, doi: 10.1007/s11432-024-4137-4
Special Topic: AI Chips and Systems for Large Language Models
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TSCompiler: efficient compilation framework for dynamic-shape models
Luo, Xiang; Zhang, Chen; Geng, Chenbo; Yi, Yanzhi; Hu, Jiahui; Zhang, Renwei; Zhang, Zhen; Consolaro, Gianpietro; Yang, Fan; Lu, Tun; Gu, Ning; Shang, Li
Sci China Inf Sci, 2024, 67(10): 200403
Keywords: machine learning; tensor compilers; dynamic shape; operator fusion; code generation; auto-tuning
Cite as: Luo X, Zhang C, Geng C B, et al. TSCompiler: efficient compilation framework for dynamic-shape models. Sci China Inf Sci, 2024, 67(10): 200403, doi: 10.1007/s11432-024-4071-6
Special Topic: AI Chips and Systems for Large Language Models
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Review of chiplet-based design: system architecture and interconnection
Liu, Yafei; Li, Xiangyu; Yin, Shouyi
Sci China Inf Sci, 2024, 67(10): 200401
Keywords: chiplet-based design; package; architecture; interconnection; silicon interposer
Cite as: Liu Y F, Li X Y, Yin S Y. Review of chiplet-based design: system architecture and interconnection. Sci China Inf Sci, 2024, 67(10): 200401, doi: 10.1007/s11432-023-3926-8
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A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique
Zhu, Zhangming; Chang, Jun; Liang, Hongzhi; Ding, Ruixue; Liu, Shubin
Sci China Inf Sci, 2024, 67(8): 189404
Keywords: Analog-to-digital converter; ADC process; PVT robustness; traveling wave; time-to-digital converter; TDC; transmission line; time domain ADC; time-interleaved
Cite as: Zhu Z M, Chang J, Liang H Z, et al. A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique. Sci China Inf Sci, 2024, 67(8): 189404, doi: 10.1007/s11432-024-4082-9
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A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS
Liu, Shubin; Han, Chenxi; Zhao, Xiaoteng; Zhang, Yuhao; Li, Shixin; Liang, Hongzhi; Yang, Lihong; Zhu, Zhangming
Sci China Inf Sci, 2024, 67(8): 189402
Keywords: Wireline Communication; Transmitter; PAM4; Adaptive retiming clock; Inverse Phase ratotor
Cite as: Liu S B, Han C X, Zhao X T, et al. A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS. Sci China Inf Sci, 2024, 67(8): 189402, doi: 10.1007/s11432-024-4072-9
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Keywords: light detection and ranging; LiDAR; time-of-flight; ToF; histogramming time-to-digital converter; hTDC; coincidence detection; analog counter
Cite as: Wu H R, Nie K M, Xu J T, et al. A column-shared histogramming TDC with pixel-to-pixel coincidence detection and compact analog counters for Flash LiDAR sensor. Sci China Inf Sci, 2024, 67(8): 189401, doi: 10.1007/s11432-024-4079-x
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A comprehensive analysis of DAC-SDC FPGA low power object detection challenge
Zhang, Jingwei; Li, Guoqing; Zhang, Meng; Cao, Xinye; Zhang, Yu; Li, Xiang; Chen, Ziyang; Yang, Jun
Sci China Inf Sci, 2024, 67(8): 182401
Keywords: tiny machine learning; object detection; convolutional neural networks; algorithm-hardware co-design; low power; field programmable gate array
Cite as: Zhang J W, Li G Q, Zhang M, et al. A comprehensive analysis of DAC-SDC FPGA low power object detection challenge. Sci China Inf Sci, 2024, 67(8): 182401, doi: 10.1007/s11432-023-3958-4
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A wide load-range OTA using a digitally assisted compensating technique
Han, Haolin; Liu, Shubin; Shen, Yi; Liang, Hongzhi; Cao, Yue; Zhong, Longjie; Zhu, Zhangming
Sci China Inf Sci, 2024, 67(7): 179402
Keywords: digital-assisted; LCD; wide load range; settling time drift; amplifier
Cite as: Han H L, Liu S B, Shen Y, et al. A wide load-range OTA using a digitally assisted compensating technique. Sci China Inf Sci, 2024, 67(7): 179402, doi: 10.1007/s11432-023-4043-9
SCIS Selected Articles on MIMO
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Keywords: adaptive bias; Doherty; linearity; PAE; SiGe BiCMOS
Cite as: Wang L, Chen J X, Hou D B, et al. A 26.5–29.5-GHz Doherty PA with enhanced linearity and efficiency based on adaptive bias circuit for 5G MIMO arrays. Sci China Inf Sci, 2024, 67(7): 179401, doi: 10.1007/s11432-024-4045-y
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CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency
Deng, Chenchen; Xiong, Tianzhu; Li, Zhaoshi; Liu, Zhiwei; Wang, Yao; Zhu, Jianfeng; Yang, Jun; Wei, Shaojun; Liu, Leibo
Sci China Inf Sci, 2024, 67(4): 149403
Keywords: Computing-in-memory; CIM; ternary contentaddressable memory; TCAM; rule update; SRAM; SDN
Cite as: Deng C C, Xiong T Z, Li Z S, et al. CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency. Sci China Inf Sci, 2024, 67(4): 149403, doi: 10.1007/s11432-023-3964-4
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Post-layout simulation driven analog circuit sizing
Gao, Xiaohan; Zhang, Haoyi; Ye, Siyuan; Liu, Mingjie; Pan, David Z.; Shen, Linxiao; Wang, Runsheng; Lin, Yibo; Huang, Ru
Sci China Inf Sci, 2024, 67(4): 142401
Keywords: analog EDA; transistor sizing; Bayesian optimization; post-layout simulation
Cite as: Gao X H, Zhang H Y, Ye S Y, et al. Post-layout simulation driven analog circuit sizing. Sci China Inf Sci, 2024, 67(4): 142401, doi: 10.1007/s11432-022-3878-5
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FSS: algorithm and neural network accelerator for style transfer
Ling, Yi; Huang, Yujie; Cai, Yujie; Li, Zhaojie; Wang, Mingyu; Li, Wenhong; Zeng, Xiaoyang
Sci China Inf Sci, 2024, 67(2): 122401
Keywords: neural network accelerator; style transfer; neural network; deep learning
Cite as: Ling Y, Huang Y J, Cai Y J, et al. FSS: algorithm and neural network accelerator for style transfer. Sci China Inf Sci, 2024, 67(2): 122401, doi: 10.1007/s11432-022-3676-2
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A Ku-band image-rejection filtering LNA MMIC in 150-nm GaN-on-SiC technology
Li, Huiyang; Xu, Jinxu; Zhang, Xiuyin
Sci China Inf Sci, 2024, 67(1): 119404
Keywords: low noise amplifier; LNA; MMIC; 150-nm GaN-on-SiC; image rejection; Ku-band
Cite as: Li H Y, Xu J X, Zhang X Y. A Ku-band image-rejection filtering LNA MMIC in 150-nm GaN-on-SiC technology. Sci China Inf Sci, 2024, 67(1): 119404, doi: 10.1007/s11432-023-3849-x